The goal of this project was to create a simple processor that could take in inputs from buttons and switches on the DELite and process that information to output information on the seven segment displays and LEDs. The processor has four main modules selected by the two buttons, and these modules each have their own four sub-modes selected by the two leftmost switches.
These four modules are arithmetic, logical, comparison, and magic. The arithmetic module takes inputs from the switches and performs addition, subtraction, multiplication, and division on them. The comparison module takes the switch inputs and performs less than, greater than, and equal to comparisons as well as printing the max of the two numbers.
A block diagram for the top level of the project can be seen below. To select the operation of the processor, the first button on the board KEY cycles through the top level modules arithmetic, logical, comparison, magic.
The left most switches SWdetermine what mode that module will be in. When using the processor, the module and mode will be shown on the middle two seven segment displays. The final module plus mode output can be seen in the truth table above. The first module that I implemented was the arithmetic module. The 8 BCD bits are split into two different 4 bit numbers to be used in addition and subtraction, but kept in tact for the multiplication and division operation.
To start off with I created a 4 bit adder by chaining 4 full adders together to create a ripple carry adder. This has 4 bit output, with each bit corresponding to the output of one of the full adders. The resulting carry is the carry produced by the final full adder. To produce the 4 bit subtracter, I did the same thing as I did with the 4 bit adder, except using full subtracters instead. In order to multiply and divide by two, I simply applied a bit shift to the 8 bit input left shift for division, right shift for multiplication.
If the multiplication function produces a carry, it is shown in the decimal point of the most significant digit, and if the division function produces a remainder it is shown in the decimal point of the least significant digit. Pictures of the output of this module on the DELite can be found in appendix A. The second module was a module that does simple logic operations. The 8 bit input is split in a similar way as it was in the arithmetic module.
This module was very straightforward in implementing, and the block diagram can be seen above. Images of results of the logic on the DELite can be found in appendix B. The third module implemented is a comparison module than compares two 4 bit integers.
The information comes in as a single 8 bit integer, but it is split up into two 4 bit integers in the same way as the previous modules. The first three modes are equal to, greater than, and less than.
The module will output a one to the seven segment display if the statement is true, and zero if false.GitHub is home to over 40 million developers working together to host and review code, manage projects, and build software together. If nothing happens, download GitHub Desktop and try again. If nothing happens, download Xcode and try again.
If nothing happens, download the GitHub extension for Visual Studio and try again. The code here is meant to be used as a starting point for using the peripheral components on the development board. Since this is wrapper code, it may or may not be functional standalone as-is. When I have time, I will endeavor to make examples more complete and wholly synthesizeable. If you try to use any part of this repository and experience problems, of if any instructions are unclear, please open an issue or contact me.
A components directory with Verilog modules, associated testbenches, and other auxiliary code if necessary. A projects directory with sample Quartus projects using the various components to demonstrate how they work in the "real world". This module is primarily for communication with the GSensor chip on the DELite board, but is hackable enough for use in other situations if needed. Allows building of more complex display based projects. The base design is targeted for the x resolution that the DELite is capable of, but is parameterized to be used at different resolutions.
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Sign up. Verilog for interacting with components of the DELite board. SystemVerilog Branch: master. Find file. Sign in Sign up. Go back.
Lesson 01: Create a New FPGA Project using Quartus Prime Standard
Launching Xcode If nothing happens, download Xcode and try again. Latest commit. Latest commit c8d6 Sep 27, Contents This repository will be split into two main subdirectories, A components directory with Verilog modules, associated testbenches, and other auxiliary code if necessary.
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Tutorial: Creating, compiling, and downloading a design into the FPGA board
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How to classify images quickly and accurately using your RPi with a camera and an internet connection.Open the project you just created using Quartus. Replace the code in the top-level module with your design implemented in verilog.
According to the manual, the two clocks are generated by the same off-chip fixed frequency clock generator, but come in on different pins on the FPGA so they should probably not be mixed without care. Note: they come out of different pins from the off chip generator.
To make your code easier to read assuming you need a clock in your designyou may like to add a wire declaration statement like the following that will allow you to use the wire "clock" for your clock signal. Since this is the clock that is used in the design, Quartus just has to ensure that its synthesized circuit can run at or faster than 50 MHz. Once this goal is achieved, Quartus can focus on other optimization goals such as using fewer CLBs or lowering power.
By increasing the specified clock frequency in the SDC file, Quartus is forced to focus more on optimizing the circuit for speed until the tools simply cannot optimize and place the circuit on the FPGA in such a way that the target clock frequency is achieved. The only change is that Quartus is given a faster timing target.
In general, if a design is able to run at a certain frequency e. The converse is not true. By default, this window will be located around the left middle of the screen. Right click on "Compile Design" and select Start. This will run the entire compilation process. A specific substep of compilation can be done by right clicking on the desired operation and selecting "Start".
Make sure you deal with any errors that occur during the compilation process.
DE10-Standard SOC FPGA dev kit.
These can be seen either in the "Processing" pane located by default at the bottom of the screen, or under "Flow Messages" in the Compilation Report. Error messages can be filtered by clicking on the red and white "X".
Every time you compile a design, look at the warnings generated. These are also found in the Flow Messages and can be filtered using the yellow triangle with a white "! Some warnings such as "Number of processors has not been specified However, other warnings such as "inferred latches" or pins not driving logic can indicate a logical flaw in the HDL that must be addressed. As part of the compilation process, Quartus performs a timing analysis on the post placed-and-routed design.
You can view the results of the timing analysis by going to Quartus' Compilation Report and expanding the menu under "TimeQuest Timing Analyzer". Quartus provides several timing reports at different operating conditions. Unless you are told otherwise, for you should use the most pessimistic slowest model which is the "Slow mV 85C Model". Expand the menu under this heading and click on the "Fmax Summary" item.
The reported clock frequency is the fastest that the current design can be clocked without violating the setup-time of any flip flops. Open the Programmer by double clicking on "Program Device" in the "Task" pane. Click "Start" to download the design to the boardOpen the Programmer by double clicking on "Program Device" in the "Task" pane. Click "Start" to download the design to the board.Jump to navigation. Whether you are an application developer, firmware engineer, hardware engineer, or enthusiast, there is a method suited for you.
There are a wealth of datasheets, user guides, tools, and other information available for the Terasic DENano. It is encouraged to review this documentation to get a deeper understanding of the system.
For this tutorial, please download and install the following first:. This means you have a complete system and can get started exploring right away by simply applying power to the board.
This method lends itself well to the scripters out there that want to do something basic and work at the file system level. This can be easily illustrated using the serial terminal.
To begin, perform the following:. The C based application will map this region into the user application space, toggle all 8 LEDs every ms for a few times, unmap the region, and exit. To begin the project, perform the following:. The DENano has a lot to offer the engineer from its capabilities, variety of tools, programming methods, and documentation.
You can take all of these concepts to the next level when you begin your next project with the DENano. He currently works on Internet of Things projects. No license express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps. The products and services described may contain defects or errors known as errata which may cause deviations from published specifications.
Current characterized errata are available on request. Copies of documents which have an order number and are referenced in this document may be obtained by calling or by visiting www. Internet of Things Documentation. Share Tweet Share Send. Prerequisites: There are a wealth of datasheets, user guides, tools, and other information available for the Terasic DENano.
Notices: No license express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document. For more complete information about compiler optimizations, see our Optimization Notice. Rate Us. Get the Newsletter.Note : After downloading the design example, you must prepare the design template. In releases After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template.
Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:.
Design Store Take a tour. IP Core Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software.
Please enable it or use sftp or scp.
Hardware Design for the Terasic DE10-Nano kit
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